245 lines
6.0 KiB
Verilog
245 lines
6.0 KiB
Verilog
`begin_keywords "1364-2005"
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/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: sqrt32synth.v,v 1.2 2007/08/30 01:25:29 stevewilliams Exp $"
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*/
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/*
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* This module approximates the square root of an unsigned 32bit
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* number. The algorithm works by doing a bit-wise binary search.
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* Starting from the most significant bit, the accumulated value
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* tries to put a 1 in the bit position. If that makes the square
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* too big for the input, the bit is left zero, otherwise it is set
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* in the result. This continues for each bit, decreasing in
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* significance, until all the bits are calculated or all the
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* remaining bits are zero.
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*
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* Since the result is an integer, this function really calculates
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* value of the expression:
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*
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* x = floor(sqrt(y))
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*
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* where sqrt(y) is the exact square root of y and floor(N) is the
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* largest integer <= N.
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*
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* For 32bit numbers, this will never run more then 16 iterations,
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* which amounts to 16 clocks.
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*/
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module sqrt
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(input clk,
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output wire rdy,
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input reset,
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input [31:0] x,
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output reg [15:0] acc);
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//32
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parameter ss=5; localparam w=1<<ss; //need to change in 2 places 1/2
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// acc holds the accumulated result, and acc2 is the accumulated
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// square of the accumulated result.
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//reg [w/2-1:0] acc;
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reg [w-1:0] acc2;
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// Keep track of which bit I'm working on.
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reg [ss-1:0] bitl;
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wire [w/2-1:0] bit = 1 << bitl;
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wire [w-1:0] bit2 = 1 << (bitl << 1);
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// The output is ready when the bitl counter underflows.
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assign rdy = bitl[ss-1];
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// guess holds the potential next values for acc, and guess2 holds
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// the square of that guess. The guess2 calculation is a little bit
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// subtle. The idea is that:
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//
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// guess2 = (acc + bit) * (acc + bit)
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// = (acc * acc) + 2*acc*bit + bit*bit
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// = acc2 + 2*acc*bit + bit2
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// = acc2 + 2 * (acc<<bitl) + bit
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//
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// This works out using shifts because bit and bit2 are known to
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// have only a single bit in them.
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wire [w/2-1:0] guess = acc | bit;
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wire [w-1:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
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(* ivl_synthesis_on *)
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always @(posedge clk or posedge reset)
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if (reset) begin
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acc = 0;
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acc2 = 0;
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bitl = w/2-1;
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end else begin
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if (guess2 <= x) begin
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acc <= guess;
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acc2 <= guess2;
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end
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bitl <= bitl - 1;
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end
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endmodule // sqrt
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module testBench;
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parameter ss=5; parameter w=1<<ss; //need to change in 2 places 2/2
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//parameter Amax= 2000000;
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parameter Amax= 10001; //quick test
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reg [w-1:0] A;
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reg clk, reset;
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wire [(w/2)-1:0] Z;
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wire done;
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sqrt dut (.clk(clk), .rdy(done), .reset(reset), .x(A), .acc(Z));
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(* ivl_synthesis_off *)
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always #5 clk = !clk;
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task reset_dut ;
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begin
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reset = 1;
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@(posedge clk);
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#1 reset = 0;
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@(negedge clk);
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end
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endtask
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task run_dut ;
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begin
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while (done==0)
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begin
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@(posedge clk);
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end
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end
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endtask
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integer idx, a, z, errCnt;
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(* ivl_synthesis_off *)
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initial
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begin
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reset = 0;
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clk = 0;
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$display ("ss=%d, width=%d, Amax=%d", ss, w, Amax);
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errCnt = 0;
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A = 4;
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reset_dut;
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run_dut;
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$display("test=0 x=%d, y=%d", A, Z);
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A = Amax/10;
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reset_dut;
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run_dut;
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$display("test=0 x=%d, y=%d", A, Z);
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A = Amax-1;
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reset_dut;
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run_dut;
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$display("test=0 x=%d, y=%d", A, Z);
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for (idx = 1 ; idx < Amax; idx = 2*idx) begin
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A = idx;
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reset_dut;
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run_dut;
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$display("%d: x=%d, y=%d", idx, A, Z);
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a = A;
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z = Z;
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if (a < (z *z)) begin
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$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
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$display("FAILED");
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$finish;
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end
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if (z<65535) // at this number y*y overflows, so cannot test this way
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begin
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if (a >= ((z + 1)*(z + 1)))
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begin
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$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
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$display("FAILED");
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$finish;
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end
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end
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else
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begin
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$display ("Could not verify above number");
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end
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end
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$display ("Running tests Amax=%d random input numbers", Amax);
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for (idx = 0 ; idx < Amax; idx = 1+ idx) begin
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A = $random;
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// A = A - ((A / Amax) * Amax); //this is needed only if <32 bit
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//A = idx; //sequential -- comment out to get random tests
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if (A < 1<<(w-1)) begin
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reset_dut;
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run_dut;
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//$display("%d: x=%d, y=%d", idx, A, Z);
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a = A;
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z = Z;
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if (a < (z *z)) begin
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$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
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$display("FAILED");
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$finish;
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end
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if (z<65535) // at this number y*y overflows, so cannot test this way
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begin
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if (a >= ((z + 1)*(z + 1)))
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begin
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$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
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$display("FAILED");
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$finish;
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end
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end
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else
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begin
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$display ("Could not verify above number");
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end
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//$display("%d: x=%d, y=%d", idx, A, Z);
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if (idx%1000 == 0) $display("Finished %d tests", idx);
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end // if (A < Amax) begin
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end
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$display ("PASSED");
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$finish;
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end
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endmodule
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`end_keywords
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