25 lines
439 B
Verilog
25 lines
439 B
Verilog
module test();
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specparam sp1 = 1;
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specparam sp2 = 2;
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specparam [3:0] sp3 = 4'b0101;
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localparam lp1 = {sp2{1'b1}};
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localparam lp2 = sp3[sp1 +: sp2];
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reg pass = 1;
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initial begin
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$display("%b", lp1);
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if (($bits(lp1) != 2) || (lp1 !== 2'b11)) pass = 0;
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$display("%b", lp2);
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if (($bits(lp2) != 2) || (lp2 !== 2'b10)) pass = 0;
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if (pass)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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