52 lines
929 B
Verilog
52 lines
929 B
Verilog
module main;
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wire dst;
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reg src;
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spec_buf dut(dst, src);
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initial begin
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src = 0;
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#10 if (dst !== 0) begin
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$display("FAILED -- setup failed: src=%b, dst=%b", src, dst);
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$finish;
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end
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src = 1;
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#5 if (dst !== 0) begin
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$display("FAILED -- dst changed too fast. src=%b, dst=%b", src, dst);
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$finish;
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end
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#5 if (dst !== 1) begin
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$display("FAILED -- dst failed to change. src=%b, dst=%b", src, dst);
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$finish;
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end
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src = 0;
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#5 if (dst !== 1) begin
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$display("FAILED -- dst changed too fast. src=%b, dst=%b", src, dst);
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$finish;
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end
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#5 if (dst !== 0) begin
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$display("FAILED -- dst failed to change. src=%b, dst=%b", src, dst);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module spec_buf(output wire O, input wire I);
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buf (O, I);
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specify
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(I => O) = (7);
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endspecify
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endmodule // sec_buf
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