96 lines
2.1 KiB
Verilog
96 lines
2.1 KiB
Verilog
/*
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* Copyright (c) 2000 Philips Semiconductors Stefan.Thiede@philips.com
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*
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* This source code is free software; you can redistribute it
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* Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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`timescale 1ns / 10ps
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`celldefine
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module MULT_8x8_f (P, A, B);
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parameter
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NA = 8,
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NB = 8,
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NP = 16,
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PX = 16'bx;
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input [NA-1:0] A;
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input [NB-1:0] B;
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output [NP-1:0] P;
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reg [NA-1:0] A_sign;
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reg [NB-1:0] B_sign;
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reg [NP-1:0] P_sign;
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reg Sign;
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wire [NA-1:0] AI;
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wire [NB-1:0] BI;
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// SDF constraint: set of buffers to allow the MIPDs annotation
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buf a0 (AI[0], A[0]);
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buf a1 (AI[1], A[1]);
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buf a2 (AI[2], A[2]);
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buf a3 (AI[3], A[3]);
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buf a4 (AI[4], A[4]);
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buf a5 (AI[5], A[5]);
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buf a6 (AI[6], A[6]);
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buf a7 (AI[7], A[7]);
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buf b0 (BI[0], B[0]);
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buf b1 (BI[1], B[1]);
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buf b2 (BI[2], B[2]);
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buf b3 (BI[3], B[3]);
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buf b4 (BI[4], B[4]);
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buf b5 (BI[5], B[5]);
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buf b6 (BI[6], B[6]);
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buf b7 (BI[7], B[7]);
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reg change_in;
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wire change_out;
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initial change_in = 0;
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buf #(0.01) bc (change_out, change_in);
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wire [NP-1:0] PI;
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// SDF constraint: P_sign cannot be used to drive directly buffers
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assign PI = P_sign;
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// SDF constraint: set of buffers to allow the output acceleration
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buf p0 (P[0], PI[0]);
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buf p1 (P[1], PI[1]);
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buf p2 (P[2], PI[2]);
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buf p3 (P[3], PI[3]);
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buf p4 (P[4], PI[4]);
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buf p5 (P[5], PI[5]);
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buf p6 (P[6], PI[6]);
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buf p7 (P[7], PI[7]);
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buf p8 (P[8], PI[8]);
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buf p9 (P[9], PI[9]);
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buf p10 (P[10], PI[10]);
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buf p11 (P[11], PI[11]);
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buf p12 (P[12], PI[12]);
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buf p13 (P[13], PI[13]);
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buf p14 (P[14], PI[14]);
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buf p15 (P[15], PI[15]);
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specify
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specparam
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th = 0.940,
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td = 4.930;
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// Pin-to-pin delay
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(A, B *> P) = (td, td, th, 0, th, 0);
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endspecify
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endmodule
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`endcelldefine
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