59 lines
1.7 KiB
Verilog
59 lines
1.7 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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//
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// Copyright (c) 1999 Steve Tell (tell@telltronics.org)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Concat in fopen not substituted correctly.
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module write_sp_vectors(Clk, a, b, c);
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input Clk, a, b, c;
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parameter fname = "PhCount.unnamed";
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parameter source_id = "(unknown source module RCSID)$";
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integer fp;
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initial
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begin
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// fails at runtime: "ERROR: $fopen parameter must be a constant"
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fp = $fopen({"work/",fname,".inv"});
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// this fails too
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// fp = $fopen({"blurfl", ".inv"});
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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$fdisplay(fp, "# captured from: %0s\n", source_id[8*80:8]);
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`else
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$fdisplay(fp, "# captured from: %0s\n", source_id[$bits(source_id)-1:8]);
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`endif
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end
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endmodule
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module main;
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parameter fname = "PhCount.unnamed";
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reg clk;
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reg a,b,c;
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write_sp_vectors #("sp2", "foo") v0 (clk,a, b, c);
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initial
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begin
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#10 $finish;
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end
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endmodule
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