35 lines
605 B
Verilog
35 lines
605 B
Verilog
module main;
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int foo, bar = 10;
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int wire_res;
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int var_res;
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assign wire_res = foo*bar;
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initial begin
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foo = 9;
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var_res = foo * bar;
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$display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res);
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if ((foo * bar) !== 90) begin
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$display("FAILED");
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$finish;
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end
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if (var_res !== 90) begin
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$display("FAILED");
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$finish;
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end
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#0; // allow CA to propagate
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$display("%0d * %0d = %0d", foo, bar, wire_res);
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if (wire_res !== 90) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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