52 lines
1.4 KiB
Verilog
52 lines
1.4 KiB
Verilog
/*
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* Copyright (c) 2000 Steve Wilson (stevew@home.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* Verify signed constant assignment to an reg.
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*/
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module test;
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integer I0,I1;
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reg [15:0] R0,R1;
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reg [3:0] error;
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initial
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begin
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R0 = -4'd12;
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R1 = -16'd12;
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error = 0;
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if(R0 !== 16'hfff4)
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begin
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$display("FAILED - negative decimal assignment failed. R0 s/b fff4, is %h",
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R0);
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error = 1;
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end
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if(R1 !== 16'hfff4)
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begin
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$display("FAILED - negative decimal assignment failed. R1 s/b fff4, is %h",
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R1);
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error = 1;
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end
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if(error === 0)
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$display("PASSED");
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end
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endmodule
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