24 lines
559 B
VHDL
24 lines
559 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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-- This is a simple test of the initialization assignment for
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-- signals. We also let a generic into the test.
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entity test is
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generic (PARM : std_logic := '0');
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port (clk : in std_logic;
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src : in std_logic;
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dst : out std_logic);
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end test;
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architecture operation of test is
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signal tmp : std_logic := PARM;
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begin
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step: process (clk)
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begin -- process step
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if clk'event and clk = '1' then -- rising clock edge
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dst <= tmp xor src;
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end if;
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end process step;
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end operation;
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