61 lines
1.5 KiB
Verilog
61 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This tests the primitive synthesis of a simple left shift.
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*/
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module test (clk,c,a,b);
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input clk;
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input a, b;
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output [1:0] c;
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reg [1:0] c;
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(* ivl_synthesis_on *)
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always @(posedge clk)
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c <= (a << 1) | b;
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endmodule
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module main;
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reg a, b, clk;
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wire [1:0] c;
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test dut (.clk(clk), .c(c), .a(a), .b(b));
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integer x;
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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for (x = 0 ; x < 4 ; x = x+1) begin
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a = x[1];
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b = x[0];
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#1 clk = 1;
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#1 clk = 0;
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if (c !== x[1:0]) begin
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$display("FAILED == x=%0d (ab=%b%b), c=%b", x, a, b, c);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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