32 lines
941 B
Verilog
32 lines
941 B
Verilog
/*
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* This example pulled from comp.lang.verilog. It was written
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* by Russell Fredrickson <russell_fredrickson@hp.com> to test
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* arithmetic shift for other compilers, and caught mine.
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*/
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module ArithmeticShiftTest;
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reg signed [31:0] in;
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reg [5:0] shift;
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reg signed [31:0] out;
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//calculate arithmetic barrel shift right
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always@(*) out = in >>> shift;
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initial begin
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//set up inputs for always block
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in = 32'sh80000000;//set to highest value negative number(-2147483648)
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shift = 6'd32; //shift the entire width of the word
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#1; //allow time for inputs to propagate
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//check output
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if(out === (32'sh80000000 >>> 6'd32)) begin
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$display("PASS: 32'sh80000000 >>> 6'd32 = 0x%h", out);
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end
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else begin
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$display("FAIL: 32'sh80000000 >>> 6'd32 != 0x%h,",
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(32'sh80000000 >>> 6'd32), " actual = 0x%h.", out);
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end
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end // initial begin
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endmodule // ArithmeticShiftTest
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