27 lines
464 B
Verilog
27 lines
464 B
Verilog
module main;
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reg [7:0] xu;
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reg signed [7:0] xs;
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initial begin
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xu = 8'b1100_0000;
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xs = 8'b1100_0000;
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xu = xu >>> 3;
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xs = xs >>> 3;
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if (xu !== 8'b0001_1000) begin
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$display("FAILED -- Unsigned >>> failed. xu=%b", xu);
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$finish;
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end
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if (xs !== 8'b1111_1000) begin
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$display("FAILED -- Signed >>> failed. xs=%b", xs);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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