44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
/*
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* Copyright (c) 2001 Stephen Rowland
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module dummy;
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reg [7:0] decode_vec;
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wire [7:0] data1;
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wire [7:0] data2;
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// icarus cant handle this statement
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assign data1 = (decode_vec[8'h02>>1] ) ? 8'h55 : 8'h00;
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assign data2 = (decode_vec[8'h01 ] ) ? 8'h55 : 8'h00;
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initial
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begin
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#0;
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$monitor("%h %h %h", decode_vec, data1, data2);
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decode_vec = 8'h02;
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#10;
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decode_vec = 8'h80;
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#10;
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decode_vec = 8'h02;
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#10;
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$finish(0);
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end
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endmodule
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