62 lines
1.5 KiB
Verilog
62 lines
1.5 KiB
Verilog
module top;
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reg pass;
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reg result;
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reg [3:0] expr;
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initial begin
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pass = 1'b1;
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result = $isunknown(1'b0);
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if (result != 0) begin
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$display("FAILED: for 1'b0 expected 0, got %b", result);
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pass = 1'b0;
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end
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result = $isunknown(1'b1);
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if (result != 0) begin
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$display("FAILED: for 1'b1 expected 0, got %b", result);
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pass = 1'b0;
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end
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result = $isunknown(2'b01);
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if (result != 0) begin
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$display("FAILED: for 2'b01 expected 0, got %b", result);
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pass = 1'b0;
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end
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result = $isunknown(4'b0x11);
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if (result != 1) begin
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$display("FAILED: for 4'b0x11 expected 1, got %b", result);
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pass = 1'b0;
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end
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expr = 4'b110x;
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result = $isunknown(expr);
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if (result != 1) begin
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$display("FAILED: for 4'b110x expected 1, got %b", result);
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pass = 1'b0;
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end
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result = $isunknown(34'bx100000000000000000000000000000001);
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if (result != 1) begin
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$display("FAILED: for 34'x100000000000000000000000000000001 expected 1, got %b", result);
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pass = 1'b0;
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end
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result = $isunknown(34'b100000000000000000000000000000000x);
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if (result != 1) begin
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$display("FAILED: for 34'100000000000000000000000000000000x expected 1, got %b", result);
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pass = 1'b0;
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end
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result = $isunknown(34'b1000000000000000000000000000000000);
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if (result != 0) begin
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$display("FAILED: for 34'1000000000000000000000000000000000 expected 0, got %b", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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