71 lines
1.9 KiB
Verilog
71 lines
1.9 KiB
Verilog
module top;
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reg pass;
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integer result;
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reg [3:0] expr;
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reg bval;
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initial begin
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pass = 1'b1;
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result = $countbits(1'bx, 1'bx);
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if (result != 1) begin
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$display("FAILED: for 1'bx/x expected a count of 1, got %d", result);
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pass = 1'b0;
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end
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result = $countbits(2'bxx, 1'bx);
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if (result != 2) begin
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$display("FAILED: for 2'bxx/x expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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result = $countbits(2'bxz, 1'bz, 1'bx);
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if (result != 2) begin
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$display("FAILED: for 2'bxz/zx expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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result = $countbits(4'b01zx, 1'bz, 1'bx);
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if (result != 2) begin
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$display("FAILED: for 4'b01zx/zx expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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result = $countbits(4'b01zx, 1'b0, 1'b1);
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if (result != 2) begin
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$display("FAILED: for 4'b01zx/01 expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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bval = 1'b0;
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expr = 4'b1001;
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result = $countbits(expr, bval);
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if (result != 2) begin
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$display("FAILED: for 4'b1001/0 expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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bval = 1'b1;
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result = $countbits(expr, bval);
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if (result != 2) begin
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$display("FAILED: for 4'b1001/1 expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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result = $countbits(34'bzx00000000000000000000000000000000, 1'bz, 1'bx);
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if (result != 2) begin
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$display("FAILED: for 34'zx00000000000000000000000000000000/zx expected a count of 2, got %d", result);
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pass = 1'b0;
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end
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result = $countbits(34'bzxxz000000xz000000xz000000xz000000, 1'bz, 1'bx);
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if (result != 10) begin
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$display("FAILED: for 34'zxxz000000xz000000xz000000xz000000/zx expected a count of 10, got %d", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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