32 lines
437 B
Verilog
32 lines
437 B
Verilog
module test1(); // bad
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initial begin
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reg a;
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for (int i=0;i<1;i++) a=1;
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end
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endmodule
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module test2(); // bad
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initial begin : block_name
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for (int i=0;i<1;i++) ;
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end
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endmodule
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module test3(); // bad
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reg a [1:0];
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initial begin : block_name
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foreach (a[i]) ;
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end
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endmodule
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module test4(); // ok
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initial begin
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for (int i=0;i<1;i++) ;
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end
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endmodule
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module stub;
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initial #100 $display("PASSED");
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endmodule // stub
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