46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
module top;
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reg pass;
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reg [7:0] in;
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reg [1:0] res;
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integer lp;
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initial begin
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pass = 1'b1;
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in = 8'b11100100;
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lp = 3;
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// lp[1:0] is being sign extended and that fails when the value mod 4
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// is either 2 or 3! A bit/part select is always unsigned unless we use
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// The $signed function to cast it to signed!
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res = in[lp[1:0]*2 +: 2];
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if (res !== 2'b11) begin
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$display("Failed expected 2'b11, got %b (%b:%d)", res, in, lp[1:0]*2);
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pass = 1'b0;
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end
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// This should give -2 for the index.
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res = in[$signed(lp[1:0])*2 +: 2];
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if (res !== 2'bxx) begin
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$display("Failed expected 2'bxx, got %b (%b:%d)", res, in,
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$signed(lp[1:0])*2);
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pass = 1'b0;
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end
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lp = 6;
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// The same as above, but not at the start of the signal.
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res = in[lp[2:1]*2 +: 2];
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if (res !== 2'b11) begin
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$display("Failed expected 2'b11, got %b (%b:%d)", res, in, lp[2:1]*2);
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pass = 1'b0;
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end
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res = in[$signed(lp[2:1])*2 +: 2];
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if (res !== 2'bxx) begin
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$display("Failed expected 2'bxx, got %b (%b:%d)", res, in,
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$signed(lp[2:1])*2);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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