50 lines
770 B
Verilog
50 lines
770 B
Verilog
module main;
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reg [7:0] mem [0:1];
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integer off;
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initial begin
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mem[0] = 8'ha5;
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mem[1] = 8'hf0;
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off = 4;
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if (mem[0] !== 8'ha5) begin
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$display("FAILED");
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$finish;
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end
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if (mem[1] !== 8'hf0) begin
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$display("FAILED");
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$finish;
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end
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if (mem[0][off+:4] !== 5'ha) begin
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$display("FAILED");
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$finish;
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end
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if (mem[1][off+:4] !== 5'hf) begin
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$display("FAILED");
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$finish;
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end
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mem[0][off +: 4] = 4'hc;
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#1 if (mem[0] !== 8'hc5) begin
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$display("FAILED");
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$finish;
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end
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mem[1][off +: 4] = 4'h3;
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#1 if (mem[1] !== 8'h30) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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