60 lines
1.4 KiB
Verilog
60 lines
1.4 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* Test the select of a bit from a parameter.
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*/
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module test;
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reg [4:0] a;
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wire o;
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RAM dut(o, a[3:0]);
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defparam test.dut.INIT = 16'h55aa;
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initial begin
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for (a = 0 ; a[4] == 0 ; a = a + 1) begin
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#1 $display("dut[%h] = %b", a, o);
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end
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end
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endmodule // test
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module RAM (O, A);
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parameter INIT = 16'h0000;
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output O;
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input [3:0] A;
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reg mem [15:0];
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reg [4:0] count;
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wire [3:0] adr;
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buf (O, mem[A]);
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initial
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begin
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for (count = 0; count < 16; count = count + 1)
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mem[count] <= INIT[count];
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end
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endmodule
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