155 lines
4.2 KiB
Verilog
155 lines
4.2 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Rewrite of stmt002_bassign.v from vbs test suite.
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//
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module main;
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reg [0:7] var1, var2; // Note the obtuse bit ordering.
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reg [3:0] var3; // A more sane ordering on a nibble boundary...
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reg var4; // Single bit.
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reg [2:9] var5; // Use a non-alligned, reversed bit - still 8 bits
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reg error;
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initial
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begin
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// First verify that all the defined variables are x's.
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error = 0;
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if(var1 !== 8'hxx)
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begin
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$display("FAILED - sdw_stmt002 - var1 not 8'hxx");
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error = 1;
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end
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if(var2 !== 8'hxx)
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begin
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$display("FAILED - sdw_stmt002 -var2 not 8'hxx");
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error = 1;
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end
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if(var3 !== 4'bx_xxx)
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begin
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$display("FAILED - sdw_stmt002 -var3 not 4'hx");
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error = 1;
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end
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if(var4 !== 1'bx)
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begin
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$display("FAILED - sdw_stmt002 -var4 not 1'bx");
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error = 1;
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end
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if(var5 !== 8'hxx)
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begin
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$display("FAILED - sdw_stmt002 -var5 not 8'hxx");
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error = 1;
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end
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var1 = 8'b1001_0010; // Do some binary bits
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var2 = 255; // Fill it with decimal version of ff
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var3 = 4'hf; // hex
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var4 = 0;
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var5 = 8'h99; // Still 8 bits
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if(var1 != 8'h92)
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begin
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$display("FAILED - sdw_stmt002 - var1 not 8'h96");
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error = 1;
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end
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if(var2 != 8'hff)
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begin
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$display("FAILED - sdw_stmt002 -var2 not 8'hff");
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error = 1;
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end
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if(var3 != 4'b1111)
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begin
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$display("FAILED - sdw_stmt002 -var3 not 4'hf");
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error = 1;
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end
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if(var4 != 1'b0)
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begin
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$display("FAILED - sdw_stmt002 -var4 not 1'b0");
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error = 1;
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end
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if(var5 != 8'h99)
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begin
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$display("FAILED - sdw_stmt002 -var5 not 8'h99");
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error = 1;
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end
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// Next - assign sub-portion of vector
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var1 [3:6] = var3;
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if(var1 != 8'h9e)
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begin
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$display("FAILED - sdw_stmt002 - subfield assign failed");
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error = 1;
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end
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var3 = 4'o11; // Lets try octal now
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var4 = 1'b1; // And set that bit to 1, it WAS 0
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var5 = 8'h66; // Invert it
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if(var3 != 4'b1001)
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begin
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$display("FAILED - sdw_stmt002 -var3 octal assign");
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error = 1;
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end
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if(var4 != 1'b1)
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begin
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$display("FAILED - sdw_stmt002 -var4 not 1'b1");
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error = 1;
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end
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if(var5 != 8'h66)
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begin
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$display("FAILED - sdw_stmt002 -var5 not 8'h66");
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error = 1;
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end
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// 9e, 9
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var3 = var1[4:7]; // Should be an 4'he
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var1[0:3] = var3[3:2]; // Now should give 8'hce
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if(var1 != 8'h3e)
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begin
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$display("FAILED - sdw_stmt002 - subfield assign(1) w/ 0 extension");
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error = 1;
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end
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if(var3 != 4'b1110)
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begin
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$display("FAILED - sdw_stmt002 -subfield assign(2)");
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error = 1;
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end
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var3 = var5; // 4 bit from 8 bit(4'h6)
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var5[5] = var4; // Set var5 to 8'h76
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if(var3 != 4'h6)
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begin
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$display("FAILED - sdw_stmt002 - 4bit from 8 bit assign");
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error = 1;
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end
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if(var5 != 8'h76)
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begin
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$display("FAILED - sdw_stmt002 - single sub-bit assign ");
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule
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