70 lines
1.7 KiB
Verilog
70 lines
1.7 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate that an lvalue concat can receive an assignment.
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//
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// D: Validate that an lvalue can be a concatenation.
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//
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module main ();
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reg a;
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reg b;
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reg working;
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initial
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begin
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working = 1;
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{a,b} = 2'b00 ;
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if( (a != 0) & (b != 0))
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begin
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$display("FAILED {a,b} Expected 2'b00 - received %b%b",a,b);
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working = 0;
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end
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{a,b} = 2'b01 ;
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if( (a != 0) & (b != 1))
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begin
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$display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b);
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working = 0;
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end
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{a,b} = 2'b10 ;
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if( (a != 1) & (b != 0))
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begin
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$display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b);
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working = 0;
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end
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{a,b} = 2'b11 ;
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if( (a != 1) & (b != 1))
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begin
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$display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b);
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working = 0;
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end
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if(working)
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$display("PASSED\n");
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end
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endmodule
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