61 lines
1.6 KiB
Verilog
61 lines
1.6 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW: function calling function validated
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//
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// D: Instantiate a 2 functions, with the 2nd calling
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// D: the first. Validate the results are correct.
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//
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module main ();
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reg [3:0] global_reg;
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reg [3:0] result;
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// Instantiate the function to be called
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function [3:0] my_func_2;
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input [3:0] a;
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begin
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my_func_2 = a;
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end
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endfunction
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// This is the calling function
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function [3:0] my_func_1 ;
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input [3:0] a;
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begin
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my_func_1 = my_func_2(a) + my_func_2(a); // So call it twice!
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end
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endfunction
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initial
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begin
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global_reg = 2;
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result = my_func_1(global_reg);
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if(result != 4)
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begin
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$display("FAILED - function didn't function!\n");
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$finish ;
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end
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$display("PASSED\n");
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$finish ;
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end
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endmodule
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