40 lines
753 B
Verilog
40 lines
753 B
Verilog
`timescale 1ns/10ps
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module top;
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reg a, pass;
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wire z;
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time edge_time;
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always @(z) begin
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if ((z === 0) && (($time - edge_time) != 3)) begin
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$display("Falling took %d, expected 3", $time - edge_time);
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pass = 1'b0;
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end
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if ((z === 1) && (($time - edge_time) != 2)) begin
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$display("Rising took %d, expected 2", $time - edge_time);
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pass = 1'b0;
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end
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end
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initial begin
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pass = 1'b1;
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$sdf_annotate("ivltests/sdf_del.sdf", top);
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#10;
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edge_time = $time;
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a = 1'b0;
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#10;
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edge_time = $time;
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a = 1'b1;
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#10 if (pass) $display("PASSED");
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end
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my_buf dut(z, a);
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endmodule
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module my_buf (output z, input a);
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buf (z, a);
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specify
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(a => z) = (0, 0);
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endspecify
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endmodule
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