35 lines
529 B
Verilog
35 lines
529 B
Verilog
module DFF (input D, input C, output reg Q);
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always @(posedge C)
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Q <= D;
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specify
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(posedge C => (Q +: D)) = (1,1);
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endspecify
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endmodule
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`endcelldefine
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module tb;
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reg clk, d;
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wire q;
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DFF dut(.D(d), .C(clk), .Q(q));
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initial begin
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clk = 0;
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d = 0;
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$monitor($time,, "D=%b, Q=%b, clk=%b", d, q, clk);
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$sdf_annotate("ivltests/sdf5.sdf");
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#10 clk = 1;
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#10 clk = 0;
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d = 1;
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#10 clk = 1;
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#10 clk = 0;
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#10 $finish(0);
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end
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endmodule // tb
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