53 lines
937 B
Verilog
53 lines
937 B
Verilog
// Copyright 2008, Martin Whitaker.
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// This file may be freely copied for any purpose.
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module sub_module();
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generate
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genvar i;
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for (i = 0; i < 4; i = i + 1) begin:gen_block
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localparam l = i + 1;
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event trigger;
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always @trigger $display("generate block %0d triggered", l);
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end
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endgenerate
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initial begin:my_block
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parameter p = 0;
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localparam l = p + 1;
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event trigger;
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@trigger $display("block %0d triggered", l);
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end
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task my_task;
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parameter p = 0;
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localparam l = p + 1;
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event trigger;
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@trigger $display("task %0d triggered", l);
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endtask
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initial my_task;
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endmodule
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module top_module();
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sub_module sub();
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defparam sub.my_block.p = 4;
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defparam sub.my_task.p = 5;
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initial begin
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#1 ->sub.gen_block[0].trigger;
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#1 ->sub.gen_block[1].trigger;
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#1 ->sub.gen_block[2].trigger;
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#1 ->sub.gen_block[3].trigger;
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#1 ->sub.my_block.trigger;
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#1 ->sub.my_task.trigger;
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#1 $finish(0);
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end
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endmodule
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