56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This test checks that the upwards search for a name stops at a
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* module boundary. In this example, the q variable in the instance
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* "inst" of the test module should be an implicit wire, even though
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* it is placed into the containing main scope that has a wire q in it.
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*/
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module test(p);
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output p;
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assign q = 1; // This should generate an error, q not defined
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assign p = q;
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endmodule // test
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module main;
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wire q = 0;
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wire sig;
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test inst(sig);
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initial begin
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#1 if (q !== 1'b0) begin
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$display("FAILED -- main.q == %b", q);
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$finish;
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end
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if (sig !== 1'b1) begin
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$display("FAILED -- main.test.q == %b", sig);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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