60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module main;
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reg a;
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reg b;
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wire q = a & b;
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initial begin
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a = 1;
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b = 0;
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#1;
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if (q !== 0) begin
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$display("FAILED -- q did not start out right: %b", q);
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$finish;
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end
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b = 1;
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if (q !== 0) begin
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// Since b takes the new value with a blocking assignment,
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// it is up to the & gate to schedule the q change, and not
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// actually push the change through.
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$display("FAILED -- q changed too soon? %b", q);
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$finish;
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end
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if (b !== 1) begin
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$display("FAILED -- b value did not stick: %b", b);
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$finish;
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end
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// The #0 delay lets the scheduler execute the change to the
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// q value, so that we can read the correct value out.
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#0 if (q !== 1) begin
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$display("FAILED -- q did not change when it should: %b", q);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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