30 lines
400 B
Verilog
30 lines
400 B
Verilog
module test;
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wire w;
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wire q;
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reg g;
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pullup(w);
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bufif1(w, 1'b1, g);
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pmos(q, w, 1'b0);
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bufif0(q, 1'b0, g);
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initial
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begin
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g = 1;
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#10
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$display(q, w); // should print "11"
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#20
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g = 0; // w changes from St1 to Pu1
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#30
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$display(q, w); // should print "01"
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if (q == 1'b0)
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$display("PASSED");
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else
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$display("FAILED");
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#40
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$finish;
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end
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endmodule
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