38 lines
587 B
Verilog
38 lines
587 B
Verilog
module top_default;
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initial begin
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$printtimescale(top_default);
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$printtimescale(top_timescale);
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$printtimescale(top_resetall);
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$printtimescale(top_timescale2);
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$printtimescale(top_timescale3);
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end
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endmodule
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`resetall
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`timescale 1ns/1ns
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module top_timescale;
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reg a;
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initial a = 1'b1;
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endmodule
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`resetall
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`resetall
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module top_resetall;
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reg a;
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initial a = 1'b0;
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endmodule
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`resetall
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`timescale 1ms/1ms
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module top_timescale2;
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reg a;
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initial a = 1'b1;
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endmodule
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`resetall
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`timescale 1us/1us
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module top_timescale3;
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reg a;
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initial a = 1'bz;
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endmodule
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