21 lines
429 B
Verilog
21 lines
429 B
Verilog
module top;
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reg pass = 1'b1;
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reg [7:0] result;
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initial begin
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result = {{0{1'b1}}, 2'b11};
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if (result != 8'h03) begin
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$display("FAILED: replication inside of concatenation");
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pass = 1'b0;
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end
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result = {2{{0{1'b1}}, 2'b11}};
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if (result != 8'h0f) begin
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$display("FAILED: replication inside of replication");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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