44 lines
688 B
Verilog
44 lines
688 B
Verilog
module recursive_func();
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function automatic [15:0] factorial;
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input [15:0] n;
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begin
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factorial = (n > 1) ? factorial(n - 1) * n : n;
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end
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endfunction
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reg [15:0] r1;
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reg [15:0] r2;
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reg [15:0] r3;
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initial begin
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fork
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r1 = factorial(3);
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r2 = factorial(4);
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r3 = factorial(5);
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join
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$display("factorial 3 = %0d", r1);
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$display("factorial 4 = %0d", r2);
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$display("factorial 5 = %0d", r3);
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end
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wire [15:0] r4;
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wire [15:0] r5;
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wire [15:0] r6;
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assign r4 = factorial(6);
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assign r5 = factorial(7);
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assign r6 = factorial(8);
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initial begin
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#1;
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$display("factorial 6 = %0d", r4);
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$display("factorial 7 = %0d", r5);
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$display("factorial 8 = %0d", r6);
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end
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endmodule
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