40 lines
678 B
Verilog
40 lines
678 B
Verilog
`timescale 1us/100ns
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module top;
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reg pass = 1'b1;
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real in1, in2;
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wire real mult;
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/* A simple multiplier. */
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assign #0.2 mult = in1*in2;
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initial begin
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#1;
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in1 = 1.0;
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in2 = 2.0;
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#1;
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if (mult != 2.0) begin
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$display("FAILED (1): expected 2.0 got %g", mult);
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pass = 0;
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end
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#1;
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in1 = 2.0;
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in2 = 1.0;
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#1;
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if (mult != 2.0) begin
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$display("FAILED (2): expected 2.0 got %g", mult);
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pass = 0;
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end
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#1;
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in1 = 1.0;
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in2 = 2.0;
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#1;
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if (mult != 2.0) begin
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$display("FAILED (3): expected 2.0 got %g", mult);
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pass = 0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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