43 lines
802 B
Verilog
43 lines
802 B
Verilog
`timescale 1us/100ns
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module top;
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reg pass = 1'b1;
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real ra = 1.0, rb = 2.0;
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wire real rmod;
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/* Real Power. */
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assign #1 rmod = ra % rb;
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initial begin
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#0.9;
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if (rmod == 1.0) begin
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pass = 1'b0;
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$display("Real: modulus value not delayed.");
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end
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#0.1;
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#0;
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if (rmod != 1.0) begin
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pass = 1'b0;
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$display("Real: modulus value not correct, expected 1.0 got %g.", rmod);
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end
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#1 ra = 2.0;
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#2;
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if (rmod != 0.0) begin
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pass = 1'b0;
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$display("Real: modulus value not correct, expected 0.0 got %g.", rmod);
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end
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#1 rb = 4.0;
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#2;
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if (rmod != 2.0) begin
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pass = 1'b0;
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$display("Real: modulus value not correct, expected 2.0 got %g.", rmod);
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end
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if (pass) $display("PASSED");
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end
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endmodule
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