70 lines
1.3 KiB
Verilog
70 lines
1.3 KiB
Verilog
module top;
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real var1, var2;
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reg [7:0] bvar;
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reg result;
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wire r_a = &var1;
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wire r_o = |var1;
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wire r_x = ^var1;
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wire r_na = ~&var1;
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wire r_no = ~|var1;
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wire r_xn1 = ~^var1;
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wire r_xn2 = ^~var1;
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wire r_b_a = var1 & var2;
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wire r_b_o = var1 | var2;
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wire r_b_x = var1 ^ var2;
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wire r_b_na = var1 ~& var2;
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wire r_b_no = var1 ~| var2;
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wire r_b_xn1 = var1 ~^ var2;
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wire r_b_xn2 = var1 ^~ var2;
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wire r_eeq = var1 === var2;
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wire r_neeq = var1 !== var2;
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wire r_ls = var1 << var2;
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wire r_als = var1 <<< var2;
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wire r_rs = var1 >> var2;
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wire r_ars = var1 >>> var2;
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wire r_con = {var1};
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wire r_rep = {2.0{var1}};
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initial begin
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var1 = 1.0;
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var2 = 2.0;
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#1;
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/* These should all fail in the compiler. */
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result = &var1;
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result = |var1;
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result = ^var1;
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result = ~&var1;
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result = ~|var1;
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result = ~^var1;
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result = ^~var1;
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result = var1 & var2;
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result = var1 | var2;
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result = var1 ^ var2;
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result = var1 ~& var2;
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result = var1 ~| var2;
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result = var1 ~^ var2;
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result = var1 ^~ var2;
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result = var1 === var2;
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result = var1 !== var2;
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bvar = var1 << var2;
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bvar = var1 <<< var2;
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bvar = var1 >> var2;
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bvar = var1 >>> var2;
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bvar = {var1};
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bvar = {2.0{var1}};
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$display("Failed");
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end
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endmodule
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