78 lines
1.9 KiB
Verilog
78 lines
1.9 KiB
Verilog
module test ();
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reg pass = 1'b1;
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reg d;
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real f = 0.0, z = 0.0, y = 1.0;
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always @(d) force f = z;
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initial begin
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// Verify the initial value.
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#1;
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if (f != 0.0) begin
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$display("Failed initial value, expected 0.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that the force changed the value and that a normal assign
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// is blocked.
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#1 d = 0;
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#1 f = 1.0;
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if (f != 0.0) begin
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$display("Failed force holding (normal), expected 0.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that an assign does not change the value when forced.
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#1 assign f = y;
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if (f != 0.0) begin
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$display("Failed force holding (assign), expected 0.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that a force will propagate.
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z = 1.0;
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#1;
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if (f != 1.0) begin
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$display("Failed force propagation, expected 1.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that the release holds the previous value.
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#1 release f;
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if (f != 1.0) begin
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$display("Failed release holding, expected 1.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that a release correctly breaks the variable link.
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#1 z = 0.0;
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if (f != 1.0) begin
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$display("Failed variable unlinking (force), expected 1.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that a deassign holds the previous value.
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#1 deassign f;
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if (f != 1.0) begin
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$display("Failed deassign holding, expected 1.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that a deassign correctly breaks the variable link.
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#1 y = 0.0;
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if (f != 1.0) begin
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$display("Failed variable unlinking (deassign), expected 1.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that the value can be changed after a release and a deassign.
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#1 f = 2.0;
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if (f != 2.0) begin
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$display("Failed release, expected 2.0, got %f", f);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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