20 lines
364 B
Verilog
20 lines
364 B
Verilog
module top;
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real rvar1, rvar2, rtmp;
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wire real wrcon3, wrcon4, wrcon5, wrcon6;
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wire real wrcon1 = {2.0, 1.0};
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wire real wrcon2 = {rvar1, rvar2};
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assign wrcon3 = {2.0, 1.0};
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assign wrcon4 = {rvar1, rvar2};
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assign {wrcon5, wrcon6} = 1.0;
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initial begin
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rtmp = {2.0, 1.0};
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rtmp = {rvar1, rvar2};
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{rvar1, rvar2} = rtmp;
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end
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endmodule
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