49 lines
1.1 KiB
Verilog
49 lines
1.1 KiB
Verilog
module test ();
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reg pass = 1'b1;
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reg d;
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real f = 0.0;
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always @(d) assign f = 0;
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initial begin
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// Verify the initial value.
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#1;
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if (f != 0.0) begin
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$display("Failed initial value, expected 0.0, got %f", f);
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pass = 1'b0;
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end
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// Verify the value can change.
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#1 f = 1.0;
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if (f != 1.0) begin
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$display("Failed value change, expected 1.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that the assign changed the value and that a normal assign
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// is blocked.
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#1 d = 0;
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#1 f = 1.0;
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if (f != 0.0) begin
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$display("Failed assign holding, expected 0.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that the release holds the previous value.
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#1 deassign f;
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if (f != 0.0) begin
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$display("Failed release holding, expected 0.0, got %f", f);
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pass = 1'b0;
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end
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// Verify that the value can be changed after a release.
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#1 f = 1.0;
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if (f != 1.0) begin
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$display("Failed release, expected 1.0, got %f", f);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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