36 lines
692 B
Verilog
36 lines
692 B
Verilog
// Check that multi-dimensional real arrays are supported
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module test;
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reg failed = 1'b0;
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`define check(expr, val) \
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if (expr != val) begin \
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$display("FAILED: `%s`, expected %f, got %f", `"expr`", val, expr); \
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failed = 1'b1; \
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end
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real r[3:0][1:0];
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integer i;
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initial begin
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for (i = 0; i < 8; i = i + 1) begin
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r[i/2][i%2] = i / 8.0 - 0.5;
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end
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`check(r[0][0], -0.5);
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`check(r[0][1], -0.375);
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`check(r[1][0], -0.25);
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`check(r[1][1], -0.125);
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`check(r[2][0], 0.0);
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`check(r[2][1], 0.125);
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`check(r[3][0], 0.25);
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`check(r[3][1], 0.375);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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