57 lines
1.2 KiB
Verilog
57 lines
1.2 KiB
Verilog
module top;
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reg pass;
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real rarr [1:0];
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real rat;
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integer i;
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wire real rmon = rarr[0];
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wire real rmonv = rarr[i];
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always @(rarr[0]) begin
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rat = rarr[0];
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end
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initial begin
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pass = 1'b1;
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i = 0;
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rarr[0] = 1.125;
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#1;
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if (rmon != 1.125) begin
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$display("Failed CA at 0, expected 1.125, got %6.3f", rmon);
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pass = 1'b0;
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end
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if (rmonv != 1.125) begin
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$display("Failed CA (var) at 0, expected 1.125, got %6.3f", rmonv);
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pass = 1'b0;
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end
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if (rat != 1.125) begin
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$display("Failed @ at 0, expected 1.125, got %6.3f", rat);
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pass = 1'b0;
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end
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rarr[0] = 2.25;
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#1;
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if (rmon != 2.25) begin
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$display("Failed CA at 1, expected 2.250, got %6.3f", rmon);
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pass = 1'b0;
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end
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if (rmonv != 2.25) begin
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$display("Failed CA (var) at 1, expected 2.250, got %6.3f", rmonv);
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pass = 1'b0;
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end
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if (rat != 2.25) begin
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$display("Failed @ at 1, expected 2.250, got %6.3f", rat);
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pass = 1'b0;
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end
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i = 1;
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#1
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if (rmonv != 0.0) begin
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$display("Failed CA (var) at 2, expected 0.000, got %6.3f", rmonv);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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