28 lines
392 B
Verilog
28 lines
392 B
Verilog
module main;
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real rfoo;
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reg [5:0] x, y;
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initial begin
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rfoo = 1.0;
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x = 5;
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y = 2;
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rfoo = rfoo + x%y;
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x = rfoo;
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$display("rfoo = %f, x=%d", rfoo, x);
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if (x !== 5'd2) begin
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$display("FAILED");
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$finish;
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end
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if (rfoo != 2.0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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