59 lines
1.5 KiB
Verilog
59 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2000 Nadim Shaikli
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/***************************************************
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*
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* Problem: Core dump on 'out of range' error
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* search for 'thing[9]'
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*
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***************************************************/
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module main;
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reg clk;
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reg [3:0] sig;
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reg [7:0] thing;
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// generate a clock
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always
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#10 clk = ~clk;
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initial
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begin
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$display ("\n<< BEGIN >>");
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case ( sig[3:0] )
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4'b0000: thing[0] = 1'b1;
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4'b0010: thing[2] = 1'b1;
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4'b0011: thing[9] = 1'b1;
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endcase // case( sig[3:0] )
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$display ("<< END >>\n");
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$finish;
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end
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// Waves definition
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// initial
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// begin
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// $dumpfile("out.dump");
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// $dumpvars(0, main);
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// end
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endmodule // main
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