64 lines
1.6 KiB
Verilog
64 lines
1.6 KiB
Verilog
/*
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* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// This example describes a 16x1 RAM that can be synthesized into
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// a CLB ram in a Xilinx FPGA.
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module ram16x1 (q, d, a, we, wclk);
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output q;
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input d;
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input [3:0] a;
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input we;
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input wclk;
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reg mem[15:0];
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assign q = mem[a];
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always @(posedge wclk) if (we) mem[a] = d;
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endmodule /* ram16x1 */
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module main;
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wire q;
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reg d;
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reg [3:0] a;
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reg we, wclk;
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ram16x1 r1 (q, d, a, we, wclk);
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initial begin
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wclk = 0;
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we = 1;
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for (a = 0 ; a < 4'hf ; a = a + 1) begin
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d = a[0];
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#1 wclk = 1;
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#1 wclk = 0;
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$display("r1[%h] == %b", a, q);
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end
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for (a = 0 ; a < 4'hf ; a = a + 1)
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#1 if (q !== a[0]) begin
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$display("FAILED -- mem[%h] !== %b", a, a[0]);
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$finish;
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end
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$display("PASSED");
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end
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endmodule /* main */
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