88 lines
2.5 KiB
Verilog
88 lines
2.5 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate the ? operator - use [var] as bit selector also
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module main;
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reg globvar;
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reg [3:0] bvec,var1,var2,var3;
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reg cond, a,b,out1,out2;
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reg error;
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initial
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begin
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error = 0;
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bvec = 4'bzx10 ;
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for(var1 = 0; var1 <= 3; var1 = var1 + 1)
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for(var2 = 0; var2 <= 3; var2 = var2 + 1)
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for(var3 = 0; var3 <= 3; var3 = var3 + 1)
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begin
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// Tried both bvec[var1] and bvec[var1:var1]
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// but believe these HAVE to be a constant expression?
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if(var1 == 4'h0)
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cond = bvec[0];
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else
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if(var1 == 4'h1)
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cond = bvec[1];
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else
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if(var1 == 4'h2)
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cond = bvec[2];
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else
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cond = bvec[3];
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if (var2 == 4'h0)
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a = bvec[0];
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else
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if (var2 == 4'h1)
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a = bvec[1];
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else
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if (var2 == 4'h2)
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a = bvec[2];
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else
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a = bvec[3];
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if (var3 == 4'h0)
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a = bvec[0];
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else
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if (var3 == 4'h1)
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a = bvec[1];
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else
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if (var3 == 4'h2)
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a = bvec[2];
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else
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a = bvec[3];
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out1 = cond ? a: b ;
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if(cond) out2 = a ;
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else out2 = b;
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if(out1 != out2)
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begin
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$display("FAILED - qmark1 - %b %b %b %b %b",
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cond,a,b,out1,out2);
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error = 1;
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end
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule // main
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