30 lines
740 B
Verilog
30 lines
740 B
Verilog
/*
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* This example is a distillation of the essence of PR#993.
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* Or at least the essence that led to a bug report.
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*/
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module main;
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integer length;
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wire [31:0] length_bits = ((length * 8 )/11)+(((length * 8 )%11) != 0);
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reg [31:0] length_bits2;
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initial begin
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for (length = 1 ; length < 56 ; length = length + 1) begin
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length_bits2 = ((length * 8 )/11)+(((length * 8 )%11) != 0);
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#1 $display("length=%3d, length_bits=%3d (%3d)",
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length, length_bits, length_bits2);
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if (length_bits != length_bits2) begin
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$display("FAILED - Expressions have different results.");
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$finish;
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end
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end // for (length = 1 ; length < 56 ; length = length + 1)
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$finish(0);
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end
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endmodule // main
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