19 lines
396 B
Verilog
19 lines
396 B
Verilog
module test();
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real r;
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initial
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begin
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r=0.25;
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$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
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r=0.5;
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$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
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$display("neg reals don't work");
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r=-0.25;
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$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
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r=-0.5;
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$write("%f %b %f\n",r, $realtobits(r), $bitstoreal($realtobits(r)));
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end
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endmodule
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