28 lines
494 B
Verilog
28 lines
494 B
Verilog
module main;
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real foo;
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initial begin
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foo = 1.0;
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if (foo != 1.0) begin
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$display("FAILED: Simple assign works not. foo=%f", foo);
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$finish;
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end
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foo <= 1.5;
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if (foo != 1.0) begin
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$display("FAILED: nb assign works too fast. foo=%f", foo);
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$finish;
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end
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#1 if (foo != 1.5) begin
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$display("FAILED: nb assign works not. foo=%f", foo);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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