42 lines
685 B
Verilog
42 lines
685 B
Verilog
/*
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* This is derived from PR#938 in the test suite.
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*/
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`timescale 1ns/100ps
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module test;
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wire out;
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reg A, B, select;
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prim_mux2 mux (out, B, A, select);
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reg [3:0] cnt;
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initial begin
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$display("A B S out");
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for (cnt = 0 ; cnt <= 'b0111 ; cnt = cnt + 1) begin
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A <= cnt[0];
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B <= cnt[1];
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select <= cnt[2];
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#1 $display("%b %b %b --> %b", A, B, select, out);
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end
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end
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endmodule
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primitive prim_mux2( output out, input in1, input in0, input select);
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table
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//in1 in0 select : out
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0 0 1 : 0;
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1 1 ? : 1;
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0 ? 1 : 0;
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1 ? 1 : 1;
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? 0 0 : 0;
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? 1 0 : 1;
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endtable
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endprimitive
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