88 lines
1.9 KiB
Verilog
88 lines
1.9 KiB
Verilog
/* I expected that p1=p2. But the generated output looks like:
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Icarus Verilog version 0.7
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Copyright 1998-2003 Stephen Williams
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$Name: $
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0 p1=x p2=StX
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5 p1=1 p2=StX
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10 p1=0 p2=St0
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15 p1=1 p2=St0
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20 p1=0 p2=St0
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25 p1=1 p2=St0
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30 p1=0 p2=St0
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35 p1=1 p2=St0
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40 p1=0 p2=St0
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45 p1=1 p2=St0
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50 p1=0 p2=St0
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55 p1=1 p2=St0
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60 p1=0 p2=St0
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65 p1=1 p2=St0
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70 p1=0 p2=St0
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75 p1=1 p2=St0
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80 p1=0 p2=St0
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85 p1=1 p2=St0
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90 p1=0 p2=St0
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95 p1=1 p2=St0
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Model Technology ModelSim SE vsim 5.7c Simulator 2003.03 Mar 13 2003
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# 0 p1=x p2=StX
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# 5 p1=1 p2=StX
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# 10 p1=0 p2=St0
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# 15 p1=1 p2=St0
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# 20 p1=0 p2=St0
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# 25 p1=1 p2=St0
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# 30 p1=0 p2=St0
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# 35 p1=1 p2=St0
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# 40 p1=0 p2=St0
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# 45 p1=1 p2=St0
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# 50 p1=0 p2=St0
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# 55 p1=1 p2=St0
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# 60 p1=0 p2=St0
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# 65 p1=1 p2=St0
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# 70 p1=0 p2=St0
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# 75 p1=1 p2=St0
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# 80 p1=0 p2=St0
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# 85 p1=1 p2=St0
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# 90 p1=0 p2=St0
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# 95 p1=1 p2=St0
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#
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*/
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`timescale 1 ns / 1 ns
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module pulse;
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reg p1,p2;
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initial
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begin
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$monitor("%t p1=%b p2=%v",$time,p1,p2);
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#101 $finish(0);
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end
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initial
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repeat(10)
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begin
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#5 p1=1'b1;
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#5 p1=1'b0;
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end
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initial
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repeat(10) single_pulse(p2);
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task single_pulse;
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output p;
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begin
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#5 p=1'b1;
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#5 p=1'b0;
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end
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endtask
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endmodule
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