39 lines
713 B
Verilog
39 lines
713 B
Verilog
module MULT32;
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wire VDD = 1 ;
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wire VSS = 0 ;
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wire X00, X31 ;
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reg [1:0] state ;
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assign {X31, X00} = state ;
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ADDERXY XX1 (VSS, N1110, VSS, N2166, X00, X31); /* This one! */
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ADDERXY XX127 (N1076, N1044, N2131, N2100, VSS, VSS);
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initial
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begin
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state = 0 ;
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$monitor( X00, X31, VSS, VSS,,, N2166, N1110 ) ;
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#10 state = 1 ;
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#10 state = 0 ;
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#10 state = 1 ;
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#10 state = 0 ;
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#10 $finish(0);
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end
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endmodule
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module ADDERXY( cin, cout, b, sum, x, y );
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input cin, b, x, y;
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output cout, sum;
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reg [1:0] total ;
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assign sum = total[0] ;
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assign cout = total[1] ;
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always @ (x or y or b or cin)
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begin
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total = ( x & y ) + b + cin ;
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end
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endmodule // ADDERXY
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