31 lines
450 B
Verilog
31 lines
450 B
Verilog
/*
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* Based on PR#904.
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* This test is part of elist, and *should* generate an
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* error.
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*/
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module err ();
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reg clk, reset_b;
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initial begin
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clk = 1'b1;
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#3 forever #10 clk=~clk;
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end
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initial begin
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reset_b = 0;
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repeat (10) @(posedge clk);
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#3 reset_b = 1;
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end
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reg [31:0] kuku;
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always @(posedge clk or negedge reset_b)
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if (~reset_b) begin
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kuku <= 0;
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end
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else begin
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kuku <= {3'd5,3'd5,,3'd5,3'd5,3'd5};
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end
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endmodule
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