23 lines
547 B
Verilog
23 lines
547 B
Verilog
/*
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* This tests some compile-time division of very long constants.
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*/
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module main;
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initial begin
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$display('h9000_0000_0000_0000_0000 / 'h3000_0000_0000_0000_0000);
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if ('h9000_0000_0000_0000_0000 / 'h3000_0000_0000_0000_0000 !== 3) begin
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$display("FAILED");
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$finish;
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end
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$display('h5000_0000_0000_0000_0000 / 'h5000_0000_0000_0000_0000);
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if ('ha000_0000_0000_0000_0000 / 'h5000_0000_0000_0000_0000 !== 2) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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